Hard Skills
AdvancedVerilog/SystemVerilogProficiency in hardware description languages used to model, simulate, and verify digital electronic systems.
ExpertStatic Timing Analysis (STA)The process of validating the timing performance of a digital circuit by checking all paths for violations without simulation.
ExpertFPGA/ASIC Implementation FlowComprehensive understanding of the design pipeline from RTL coding to synthesis, floorplanning, and place-and-route.
AdvancedLow-Power Design TechniquesThe application of methods such as clock gating and power-domain partitioning to minimize energy consumption in digital circuits.
AdvancedUVM (Universal Verification Methodology)A standardized methodology for verifying integrated circuit designs using SystemVerilog classes and testbench structures.
IntermediatePCB Layout DesignDesigning the physical arrangement of components and traces on a printed circuit board to ensure electrical integrity.