Hard Skills
AdvancedRTL DesignThe process of creating a high-level digital logic design using hardware description languages like Verilog or SystemVerilog.
AdvancedStatic Timing Analysis (STA)A method of computing the expected timing of a digital circuit without requiring simulation of the full circuit.
IntermediateDesign for Testability (DFT)Techniques added to a chip design to make it easier to test the manufactured hardware for defects.
ExpertFunctional VerificationThe use of simulation and formal methods to ensure that the ASIC design meets its specified requirements.
AdvancedSynthesis and Place-and-RouteThe conversion of RTL code into a gate-level netlist and the subsequent mapping to physical locations on the chip.